| Program Detail |
: This course consists of an in-depth study of principles and practice of scale-driven CMOS front and back end processing. Front end pro- cessing involves steps up to the fabrication of active devices that include wells, isolation, gate insulator, gate electrode, and source/ drain formation. Many device effects observed in submicron MOSFETs are impacted by the process technology used to fabricate them. Some effects include small dimension effects, punch-throughm threshold ad- justment, latch up, gate leakage and depletion effects and quantum effects. MOSFET structures, materials and process technology dev- eloped to combat these effects will be discussed as well as back end interconnect technology. Topics include interconnet modeling and de- lay. Low-k dielectric and copper damascene processes will be studied. Intro to Semicond. Ind. Assoc. (SIA) International Technology Roadmap for Semicond. (ITRS) (0305-560, 701, 702, 703) Class 4, Lab 0, Cred. 4 |
